tests/various/bug2014.ys

   1 read_verilog <<EOT
   2 module test (
   3         input signed [1:0] n,
   4         output [3:0] dout
   5 );
   6         assign dout = n + 4'sd 4;
   7 endmodule
   8 EOT
   9
  10 alumacc
  11 select -assert-count 1 t:$alu
  12 equiv_opt -assert opt -fine