Merge pull request #2576 from zachjs/port-bind-sign-uniop
[yosys.git] / tests / various / const_arg_loop.v
1 module top;
2 function automatic [31:0] operation1;
3 input [4:0] rounds;
4 input integer num;
5 integer i;
6 begin
7 begin : shadow
8 integer rounds;
9 rounds = 0;
10 end
11 for (i = 0; i < rounds; i = i + 1)
12 num = num * 2;
13 operation1 = num;
14 end
15 endfunction
16
17 function automatic [31:0] pass_through;
18 input [31:0] inp;
19 pass_through = inp;
20 endfunction
21
22 function automatic [31:0] operation2;
23 input [4:0] var;
24 input integer num;
25 begin
26 var[0] = var[0] ^ 1;
27 operation2 = num * var;
28 end
29 endfunction
30
31 function automatic [31:0] operation3;
32 input [4:0] rounds;
33 input integer num;
34 reg [4:0] rounds;
35 integer i;
36 begin
37 begin : shadow
38 integer rounds;
39 rounds = 0;
40 end
41 for (i = 0; i < rounds; i = i + 1)
42 num = num * 2;
43 operation3 = num;
44 end
45 endfunction
46
47 function automatic [16:0] operation4;
48 input [15:0] a;
49 input b;
50 operation4 = {a, b};
51 endfunction
52
53 function automatic integer operation5;
54 input x;
55 integer x;
56 operation5 = x;
57 endfunction
58
59 wire [31:0] a;
60 assign a = 2;
61
62 parameter A = 3;
63
64 wire [31:0] x1;
65 assign x1 = operation1(A, a);
66
67 wire [31:0] x1b;
68 assign x1b = operation1(pass_through(A), a);
69
70 wire [31:0] x2;
71 assign x2 = operation2(A, a);
72
73 wire [31:0] x3;
74 assign x3 = operation3(A, a);
75
76 wire [16:0] x4;
77 assign x4 = operation4(a[15:0], 0);
78
79 wire [31:0] x5;
80 assign x5 = operation5(64);
81
82 // `define VERIFY
83 `ifdef VERIFY
84 assert property (a == 2);
85 assert property (A == 3);
86 assert property (x1 == 16);
87 assert property (x1b == 16);
88 assert property (x2 == 4);
89 assert property (x3 == 16);
90 assert property (x4 == a << 1);
91 assert property (x5 == 64);
92 `endif
93 endmodule