genrtlil: fix mux2rtlil generated wire signedness
[yosys.git] / tests / various / constcomment.ys
1 read_verilog <<EOT
2 module top1;
3 localparam a = 8 /*foo*/ 'h ab;
4 localparam b = 8 'h /*foo*/ cd;
5 generate
6 if (a != 8'b10101011) $error("a incorrect!");
7 if (b != 8'b11001101) $error("b incorrect!");
8 endgenerate
9 endmodule
10 EOT
11 logger -expect error "syntax error, unexpected TOK_BASE" 1
12 read_verilog <<EOT
13 module top2;
14 localparam a = 12'h4 /*foo*/'b0;
15 endmodule
16 EOT