tests/various/design2.ys

   1 read_verilog <<EOT
   2 module top(input i, output o);
   3 assign o = i;
   4 endmodule
   5 EOT
   6 design -stash foo
   7 design -delete foo
   8 logger -expect error "No saved design 'foo' found!" 1
   9 design -load foo