tests/various/equiv_opt_multiclock.ys

   1 read_verilog <<EOT
   2 module top(input clk, pre, d, output reg q);
   3         always @(posedge clk, posedge pre)
   4                 if (pre)
   5                         q <= 1'b1;
   6                 else
   7                         q <= d;
   8 endmodule
   9 EOT
  10
  11 prep
  12 equiv_opt -assert -multiclock -map +/simcells.v synth