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verilog: significant block scoping improvements
[yosys.git]
/
tests
/
various
/
gen_if_null.v
1
`default_nettype none
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module test;
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localparam OFF = 0;
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generate
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if (OFF) ;
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else wire x;
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if (!OFF) wire y;
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else ;
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if (OFF) ;
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else ;
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if (OFF) ;
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wire z;
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endgenerate
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assign genblk1.x = 0;
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assign genblk2.y = 0;
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assign z = 0;
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endmodule