verilog: significant block scoping improvements
[yosys.git] / tests / various / gen_if_null.v
1 `default_nettype none
2 module test;
3 localparam OFF = 0;
4 generate
5 if (OFF) ;
6 else wire x;
7 if (!OFF) wire y;
8 else ;
9 if (OFF) ;
10 else ;
11 if (OFF) ;
12 wire z;
13 endgenerate
14 assign genblk1.x = 0;
15 assign genblk2.y = 0;
16 assign z = 0;
17 endmodule