Merge pull request #941 from Wren6991/sim_lib_io_clke
[yosys.git] / tests / various / hierarchy.sh
1 #!/usr/bin/env bash
2 # Simple test of hierarchy -auto-top.
3
4 set -e
5
6 echo -n " TOP first - "
7 ../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
8 read_verilog << EOV
9 module TOP(a, y);
10 input a;
11 output [31:0] y;
12
13 aoi12 p [31:0] (a, y);
14 endmodule
15
16 module aoi12(a, y);
17 input a;
18 output y;
19 assign y = ~a;
20 endmodule
21 EOV
22 hierarchy -auto-top
23 EOY
24
25 echo -n " TOP last - "
26 ../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
27 read_verilog << EOV
28 module aoi12(a, y);
29 input a;
30 output y;
31 assign y = ~a;
32 endmodule
33
34 module TOP(a, y);
35 input a;
36 output [31:0] y;
37
38 aoi12 foo (a, y);
39 endmodule
40 EOV
41 hierarchy -auto-top
42 EOY
43
44 echo -n " no explicit top - "
45 ../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
46 read_verilog << EOV
47 module aoi12(a, y);
48 input a;
49 output y;
50 assign y = ~a;
51 endmodule
52
53 module noTop(a, y);
54 input a;
55 output [31:0] y;
56 assign y = a;
57 endmodule
58 EOV
59 hierarchy -auto-top
60 EOY