tests/various/logic_param_simple.ys

   1 read_verilog -sv <<EOT
   2 module test_logic_param();
   3 parameter logic                 a = 0;
   4 parameter logic [31:0]          e = 0;
   5 parameter logic signed          b = 0;
   6 parameter logic unsigned        c = 0;
   7 parameter logic unsigned [31:0] d = 0;
   8 endmodule
   9 EOT