tests/various/mem2reg.ys

   1 read_verilog <<EOT
   2 module top;
   3 parameter DATADEPTH=2;
   4 parameter DATAWIDTH=1;
   5 (* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
   6 (* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
   7 endmodule
   8 EOT
   9
  10 proc
  11 cd top
  12 select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i
  13 select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i
  14 select -assert-none a:mem2reg