tests/various/muxcover.ys

   1
   2 read_verilog -formal <<EOT
   3     module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
   4         always @*
   5             (* parallel_case *)
   6             casez (X)
   7                 3'b??1: Y = A;
   8                 3'b?1?: Y = B;
   9                 3'b1??: Y = C;
  10                 3'b000: Y = D;
  11             endcase
  12     endmodule
  13 EOT
  14
  15
  16 ## Examle usage for "pmuxtree" and "muxcover"
  17
  18 proc
  19 pmuxtree
  20 techmap
  21 muxcover -mux4
  22
  23 splitnets -ports
  24 clean
  25 # show
  26
  27
  28 ## Equivalence checking
  29
  30 read_verilog -formal <<EOT
  31     module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
  32         always @*
  33             casez (X)
  34                 3'b001: Y = A;
  35                 3'b010: Y = B;
  36                 3'b100: Y = C;
  37                 3'b000: Y = D;
  38                 default: Y = 'bx;
  39             endcase
  40     endmodule
  41 EOT
  42
  43 proc
  44 splitnets -ports
  45 techmap -map +/simcells.v t:$_MUX4_
  46
  47 equiv_make gold gate equiv
  48 hierarchy -top equiv
  49 equiv_simple -undef
  50 equiv_status -assert
  51