tests/various/muxcover.ys

   1
   2 read_verilog -formal <<EOT
   3     module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
   4         always @*
   5             (* parallel_case *)
   6             casez (X)
   7                 3'b??1: Y = A;
   8                 3'b?1?: Y = B;
   9                 3'b1??: Y = C;
  10                 3'b000: Y = D;
  11                 default: Y = 'bx;
  12             endcase
  13     endmodule
  14 EOT
  15
  16
  17 ## Example usage for "pmuxtree" and "muxcover"
  18
  19 proc
  20 pmuxtree
  21 techmap
  22 muxcover -mux4
  23
  24 splitnets -ports
  25 clean
  26 # show
  27
  28
  29 ## Equivalence checking
  30
  31 read_verilog -formal <<EOT
  32     module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
  33         always @*
  34             casez (X)
  35                 3'b001: Y = A;
  36                 3'b010: Y = B;
  37                 3'b100: Y = C;
  38                 3'b000: Y = D;
  39                 default: Y = 'bx;
  40             endcase
  41     endmodule
  42 EOT
  43
  44 proc
  45 splitnets -ports
  46 techmap -map +/simcells.v t:$_MUX4_
  47
  48 equiv_make gold gate equiv
  49 hierarchy -top equiv
  50 equiv_simple -undef
  51 equiv_status -assert
  52