2 read_verilog -formal <<EOT
3 module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
17 ## Example usage for "pmuxtree" and "muxcover"
29 ## Equivalence checking
31 read_verilog -formal <<EOT
32 module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
46 techmap -map +/simcells.v t:$_MUX4_
48 equiv_make gold gate equiv