1 module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
3 if (s == 0) o <= i[0*W+:W];
4 else if (s == 1) o <= i[1*W+:W];
5 else if (s == 2) o <= i[2*W+:W];
6 else if (s == 3) o <= i[3*W+:W];
10 module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
13 if (s == 0) o <= i[0*W+:W];
14 if (s == 1) o <= i[1*W+:W];
15 if (s == 2) o <= i[2*W+:W];
16 if (s == 3) o <= i[3*W+:W];
17 if (s == 4) o <= i[4*W+:W];
21 module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
27 if (s != 4) o <= i[4*W+:W];
35 module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
38 if (s == 0) o <= i[0*W+:W];
39 if (s == 1) o <= i[1*W+:W];
40 if (s == 2) o[W-2:0] <= i[2*W+:W-1];
41 if (s == 3) o <= i[3*W+:W];
42 if (s == 4) o <= i[4*W+:W];
46 module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
48 if (s == 0) o <= i[0*W+:W];
49 // else if (s == 1) o <= i[1*W+:W];
50 // else if (s == 2) o <= i[2*W+:W];
51 else if (s == 3) o <= i[3*W+:W];
56 module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
59 if (s == 3) o <= i[3*W+:W];
60 if (s == 2) o <= i[2*W+:W];
61 if (s == 1) o <= i[1*W+:W];
62 if (s == 4) o <= i[4*W+:W];
63 if (s == 0) o <= i[0*W+:W];
67 module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
69 if (s == 0) o <= i[0*W+:W];
70 else if (s == 1) o <= i[1*W+:W];
71 else if (s == 2) o <= i[2*W+:W];
72 else if (s == 3) o <= i[3*W+:W];
73 else if (s == 0) o <= {W{1'b0}};
77 module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
80 if (s == 0) o <= i[0*W+:W];
81 if (s == 1) o <= i[1*W+:W];
82 if (s == 2) o <= i[2*W+:W];
83 if (s == 3) o <= i[3*W+:W];
84 if (s == 4) o <= i[4*W+:W];
85 if (s == 0) o <= i[2*W+:W];
89 module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
106 default: o <= i[7*W+:W];
114 module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
140 module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);