tests/various/printattr.ys

   1 logger -expect log ".*cells_not_processed=[01]* .*" 1
   2 logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
   3 read_verilog <<EOT
   4 module mux2(a, b, s, y);
   5         input a, b, s;
   6         output y;
   7
   8         wire s_n = ~s;
   9         wire t0 = s & a;
  10         wire t1 = s_n & b;
  11         assign y = t0 | t1;
  12 endmodule
  13 EOT
  14 printattrs