tests/various/reg_wire_error.sv

   1 module sub_mod(input i_in, output o_out);
   2 assign o_out = i_in;
   3 endmodule
   4
   5 module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
   6 input i_clk;
   7 input i;
   8 input i_reg;
   9 output o_reg;
  10 output o_wire;
  11 output o_mr, o_mw, o_ml;
  12
  13 // Enable this to see how it doesn't fail on yosys although it should
  14 //reg o_wire;
  15 // Enable this instead of the above to see how logic can be mapped to a wire
  16 logic o_wire;
  17 // Enable this to see how it doesn't fail on yosys although it should
  18 //reg i_reg;
  19 // Disable this to see how it doesn't fail on yosys although it should
  20 //reg o_reg;
  21
  22 logic l_reg;
  23
  24 // Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
  25 assign l_reg = !o_reg;
  26 initial o_reg = 1'b0;
  27 always @(posedge i_clk)
  28 begin
  29   o_reg <= !o_reg;
  30   l_reg <= !o_reg;
  31 end
  32
  33 assign o_wire = !o_reg;
  34 // Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
  35 assign l_reg = !o_reg;
  36
  37 sub_mod sm_inst (
  38   .i_in(1'b1),
  39   .o_out(o_reg)
  40 );
  41
  42 wire   mw1[0:1];
  43 wire   mw2[0:1];
  44 wire   mw3[0:1];
  45 reg    mr1[0:1];
  46 reg    mr2[0:1];
  47 reg    mr3[0:1];
  48 logic  ml1[0:1];
  49 logic  ml2[0:1];
  50 logic  ml3[0:1];
  51
  52 assign o_mw = mw1[i];
  53 assign o_mr = mr1[i];
  54 assign o_ml = ml1[i];
  55
  56 assign mw1[1] = 1'b1;
  57 //assign mr1[1] = 1'b1;
  58 assign ml1[1] = 1'b1;
  59 always @(posedge i_clk)
  60 begin
  61   mr2[0] = 1'b0;
  62   mw2[0] = 1'b0;
  63   ml2[0] = 1'b0;
  64 end
  65
  66 always @(posedge i_clk)
  67 begin
  68   mr3[0] <= 1'b0;
  69   mw3[0] <= 1'b0;
  70   ml3[0] <= 1'b0;
  71 end
  72
  73 endmodule
  74