1 module sub_mod(input i_in, output o_out);
5 module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
11 output o_mr, o_mw, o_ml;
13 // Enable this to see how it doesn't fail on yosys although it should
15 // Enable this instead of the above to see how logic can be mapped to a wire
17 // Enable this to see how it doesn't fail on yosys although it should
19 // Disable this to see how it doesn't fail on yosys although it should
24 // Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
25 assign l_reg = !o_reg;
27 always @(posedge i_clk)
33 assign o_wire = !o_reg;
34 // Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
35 assign l_reg = !o_reg;
57 //assign mr1[1] = 1'b1;
59 always @(posedge i_clk)
66 always @(posedge i_clk)