tests/various/script.ys

   1 read_verilog -formal <<EOT
   2     module top;
   3         foo bar();
   4         foo asdf();
   5         winnie the_pooh();
   6
   7         wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
   8         wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
   9     endmodule
  10
  11     module other;
  12         wire [1023:0] _DELETE = "cd; delete c:bar";
  13     endmodule
  14 EOT
  15
  16 script -scriptwire w:_RUNME*
  17
  18 select w:_DELETE
  19 script -scriptwire
  20 select -assert-count 1 t:foo