tests/various/shregmap.v

   1 module shregmap_static_test(input i, clk, output [1:0] q);
   2 reg head = 1'b0;
   3 reg [3:0] shift1 = 4'b0000;
   4 reg [3:0] shift2 = 4'b0000;
   5
   6 always @(posedge clk) begin
   7     head <= i;
   8     shift1 <= {shift1[2:0], head};
   9     shift2 <= {shift2[2:0], head};
  10 end
  11
  12 assign q = {shift2[3], shift1[3]};
  13 endmodule
  14
  15 module $__SHREG_DFF_P_(input C, D, output Q);
  16 parameter DEPTH = 1;
  17 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
  18 reg [DEPTH-1:0] r = INIT;
  19 always @(posedge C)
  20     r <= { r[DEPTH-2:0], D };
  21 assign Q = r[DEPTH-1];
  22 endmodule
  23
  24 module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
  25 reg head = 1'b0;
  26 reg [3:0] shift1 = 4'b0000;
  27 reg [3:0] shift2 = 4'b0000;
  28
  29 always @(posedge clk) begin
  30     head <= i;
  31     shift1 <= {shift1[2:0], head};
  32     shift2 <= {shift2[2:0], head};
  33 end
  34
  35 assign q = {shift2[l2], shift1[l1]};
  36 endmodule
  37
  38 module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
  39 parameter CLKPOL = 1;
  40 parameter ENPOL = 1;
  41 parameter DEPTH = 1;
  42 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
  43 reg [DEPTH-1:0] r = INIT;
  44 wire clk = C ^ CLKPOL;
  45 always @(posedge C)
  46     r <= { r[DEPTH-2:0], D };
  47 assign Q = r[L];
  48 endmodule