1 read_verilog shregmap.v
4 design -copy-to model $__SHREG_DFF_P_
5 hierarchy -top shregmap_static_test
16 select -assert-count 1 t:$_DFF_P_
17 select -assert-count 2 t:$__SHREG_DFF_P_
21 design -import gold -as gold
22 design -import gate -as gate
23 design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
26 miter -equiv -flatten -make_assert -make_outputs gold gate miter
27 sat -verify -prove-asserts -show-ports -seq 5 miter