tests/various/signed.ys

   1 # SV LRM A2.2.1
   2
   3 read_verilog -sv <<EOT
   4 module test_signed();
   5 parameter integer signed  a = 0;
   6 parameter integer unsigned  b = 0;
   7
   8 endmodule
   9 EOT
  10
  11 design -reset
  12 read_verilog -sv <<EOT
  13 module test_signed();
  14 parameter logic signed [7:0] a = 0;
  15 parameter logic unsigned [7:0] b = 0;
  16
  17 endmodule
  18 EOT
  19
  20 design -reset
  21 logger -expect error "syntax error, unexpected TOK_INTEGER" 1
  22 read_verilog -sv <<EOT
  23 module test_signed();
  24 parameter signed integer a = 0;
  25 parameter unsigned integer b = 0;
  26
  27 endmodule
  28 EOT