tests/various/sim_const.ys

   1 read_verilog <<EOT
   2
   3 module top(input clk, output reg [1:0] q);
   4         wire [1:0] x = 2'b10;
   5         always @(posedge clk)
   6                 q <= x & 2'b11;
   7 endmodule
   8 EOT
   9
  10 proc
  11 sim -clock clk -n 1 -w top
  12 select -assert-count 1 a:init=2'b10 top/q %i
  13