Fix wire width
[yosys.git] / tests / various / specify.v
1 module test (
2 input EN, CLK,
3 input [3:0] D,
4 output reg [3:0] Q
5 );
6 always @(posedge CLK)
7 if (EN) Q <= D;
8
9 specify
10 `ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
11 if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
12 $setup(D, posedge CLK &&& EN, 5);
13 $hold(posedge CLK, D &&& EN, 6);
14 `endif
15 endspecify
16 endmodule
17
18 module test2 (
19 input A, B,
20 output Q
21 );
22 xor (Q, A, B);
23 specify
24 //specparam T_rise = 1;
25 //specparam T_fall = 2;
26 `define T_rise 1
27 `define T_fall 2
28 (A => Q) = (`T_rise,`T_fall);
29 //(B => Q) = (`T_rise+`T_fall)/2.0;
30 (B => Q) = 1.5;
31 endspecify
32 endmodule
33
34 module issue01144(input clk, d, output q);
35 specify
36 (posedge clk => (q +: d)) = (3,1);
37 (posedge clk *> (q +: d)) = (3,1);
38 endspecify
39 endmodule