Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
[yosys.git] / tests / various / specify.v
1 module test (
2 input EN, CLK,
3 input [3:0] D,
4 output reg [3:0] Q
5 );
6 always @(posedge CLK)
7 if (EN) Q <= D;
8
9 specify
10 if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
11 $setup(D, posedge CLK &&& EN, 5);
12 $hold(posedge CLK, D &&& EN, 6);
13 endspecify
14 endmodule
15
16 module test2 (
17 input A, B,
18 output Q
19 );
20 xor (Q, A, B);
21 specify
22 //specparam T_rise = 1;
23 //specparam T_fall = 2;
24 `define T_rise 1
25 `define T_fall 2
26 (A => Q) = (`T_rise,`T_fall);
27 //(B => Q) = (`T_rise+`T_fall)/2.0;
28 (B => Q) = 1.5;
29 endspecify
30 endmodule