tests/various/specify.v

   1 module test (
   2         input EN, CLK,
   3         input [3:0] D,
   4         output reg [3:0] Q
   5 );
   6         always @(posedge CLK)
   7                 if (EN) Q <= D;
   8
   9         specify
  10                 if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
  11                 $setup(D, posedge CLK &&& EN, 5);
  12                 $hold(posedge CLK, D &&& EN, 6);
  13         endspecify
  14 endmodule
  15
  16 module test2 (
  17         input A, B,
  18         output Q
  19 );
  20         xor (Q, A, B);
  21         specify
  22                 //specparam T_rise = 1;
  23                 //specparam T_fall = 2;
  24                 `define T_rise 1
  25                 `define T_fall 2
  26                 (A => Q) = (`T_rise,`T_fall);
  27                 //(B => Q) = (`T_rise+`T_fall)/2.0;
  28                 (B => Q) = 1.5;
  29         endspecify
  30 endmodule
  31
  32 module issue01144(input clk, d, output q);
  33 specify
  34   (posedge clk => (q +: d)) = (3,1);
  35   (posedge clk *> (q +: d)) = (3,1);
  36 endspecify
  37 endmodule
  38
  39 module test3(input clk, input [1:0] d, output [1:0] q);
  40 specify
  41   (posedge clk => (q +: d)) = (3,1);
  42   (posedge clk *> (q +: d)) = (3,1);
  43 endspecify
  44 endmodule
  45
  46 module test4(input clk, d, output q);
  47 specify
  48   $setup(d, posedge clk, 1:2:3);
  49   $setuphold(d, posedge clk, 1:2:3, 4:5:6);
  50 endspecify
  51 endmodule
  52
  53 module test5(input clk, d, e, output q);
  54 specify
  55   $setup(d, posedge clk &&& e, 1:2:3);
  56 endspecify
  57 endmodule
  58
  59 module test6(input clk, d, e, output q);
  60 specify
  61   (d[0] *> q[0]) = (3,1);
  62   (posedge clk[0] => (q[0] +: d[0])) = (3,1);
  63 endspecify
  64 endmodule