tests/various/specify.ys

   1 read_verilog -specify specify.v
   2 prep
   3 cd test
   4 select t:$specify2 -assert-count 0
   5 select t:$specify3 -assert-count 1
   6 select t:$specrule -assert-count 2
   7 cd test2
   8 select t:$specify2 -assert-count 2
   9 select t:$specify3 -assert-count 0
  10 select t:$specrule -assert-count 0
  11 cd
  12 write_verilog specify.out
  13 design -stash gold
  14
  15 read_verilog -specify specify.out
  16 prep
  17 cd test
  18 select t:$specify2 -assert-count 0
  19 select t:$specify3 -assert-count 1
  20 select t:$specrule -assert-count 2
  21 cd test2
  22 select t:$specify2 -assert-count 2
  23 select t:$specify3 -assert-count 0
  24 select t:$specrule -assert-count 0
  25 cd
  26 design -stash gate
  27
  28 design -copy-from gold -as gold test
  29 design -copy-from gate -as gate test
  30 rename -hide
  31 rename -enumerate -pattern A_% t:$specify3
  32 rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
  33 rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
  34 select n:A_* -assert-count 2
  35 select n:B_* -assert-count 2
  36 select n:C_* -assert-count 2
  37 equiv_make gold gate equiv
  38 hierarchy -top equiv
  39 equiv_struct
  40 equiv_induct -seq 5
  41 equiv_status -assert
  42 design -reset
  43
  44 design -copy-from gold -as gold test2
  45 design -copy-from gate -as gate test2
  46 rename -hide
  47 rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
  48 rename -enumerate -pattern B_% t:$specify2 n:A_* %d
  49 select n:A_* -assert-count 2
  50 select n:B_* -assert-count 2
  51 equiv_make gold gate equiv
  52 hierarchy -top equiv
  53 equiv_struct
  54 equiv_induct -seq 5
  55 equiv_status -assert
  56 design -reset
  57
  58 read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v