1 read_verilog -specify specify.v
4 select t:$specify2 -assert-count 0
5 select t:$specify3 -assert-count 1
6 select t:$specrule -assert-count 2
7 select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
8 select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
9 select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
11 select t:$specify2 -assert-count 2
12 select t:$specify3 -assert-count 0
13 select t:$specrule -assert-count 0
14 select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
15 # ^^ Note use of macro
16 select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
18 write_verilog specify.out
21 read_verilog -specify specify.out
24 select t:$specify2 -assert-count 0
25 select t:$specify3 -assert-count 1
26 select t:$specrule -assert-count 2
28 select t:$specify2 -assert-count 2
29 select t:$specify3 -assert-count 0
30 select t:$specrule -assert-count 0
34 design -copy-from gold -as gold test
35 design -copy-from gate -as gate test
37 rename -enumerate -pattern A_% t:$specify3
38 rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
39 rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
40 select n:A_* -assert-count 2
41 select n:B_* -assert-count 2
42 select n:C_* -assert-count 2
43 equiv_make gold gate equiv
50 design -copy-from gold -as gold test2
51 design -copy-from gate -as gate test2
53 rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
54 rename -enumerate -pattern B_% t:$specify2 n:A_* %d
55 select n:A_* -assert-count 2
56 select n:B_* -assert-count 2
57 equiv_make gold gate equiv
64 read_verilog -specify <<EOT
66 module test7_sub(input i, output o);
73 module test7(input i, output o);
75 test7_sub unused(i, w);
82 select -assert-count 1 c:used
83 select -assert-none c:* c:used %d