tests/various/specify.ys

   1 read_verilog -specify specify.v
   2 prep
   3 cd test
   4 select t:$specify2 -assert-count 0
   5 select t:$specify3 -assert-count 1
   6 select t:$specrule -assert-count 2
   7 select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
   8 select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
   9 select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
  10 cd test2
  11 select t:$specify2 -assert-count 2
  12 select t:$specify3 -assert-count 0
  13 select t:$specrule -assert-count 0
  14 select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
  15                                          # ^^ Note use of macro
  16 select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
  17 cd
  18 write_verilog specify.out
  19 design -stash gold
  20
  21 read_verilog -specify specify.out
  22 prep
  23 cd test
  24 select t:$specify2 -assert-count 0
  25 select t:$specify3 -assert-count 1
  26 select t:$specrule -assert-count 2
  27 cd test2
  28 select t:$specify2 -assert-count 2
  29 select t:$specify3 -assert-count 0
  30 select t:$specrule -assert-count 0
  31 cd
  32 design -stash gate
  33
  34 design -copy-from gold -as gold test
  35 design -copy-from gate -as gate test
  36 rename -hide
  37 rename -enumerate -pattern A_% t:$specify3
  38 rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
  39 rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
  40 select n:A_* -assert-count 2
  41 select n:B_* -assert-count 2
  42 select n:C_* -assert-count 2
  43 equiv_make gold gate equiv
  44 hierarchy -top equiv
  45 equiv_struct
  46 equiv_induct -seq 5
  47 equiv_status -assert
  48 design -reset
  49
  50 design -copy-from gold -as gold test2
  51 design -copy-from gate -as gate test2
  52 rename -hide
  53 rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
  54 rename -enumerate -pattern B_% t:$specify2 n:A_* %d
  55 select n:A_* -assert-count 2
  56 select n:B_* -assert-count 2
  57 equiv_make gold gate equiv
  58 hierarchy -top equiv
  59 equiv_struct
  60 equiv_induct -seq 5
  61 equiv_status -assert
  62 design -reset
  63
  64 read_verilog -specify <<EOT
  65 (* blackbox *)
  66 module test7_sub(input i, output o);
  67 specify
  68     (i => o) = 1;
  69 endspecify
  70 assign o = ~i;
  71 endmodule
  72
  73 module test7(input i, output o);
  74     wire w;
  75     test7_sub unused(i, w);
  76     test7_sub used(i, o);
  77 endmodule
  78 EOT
  79 hierarchy
  80 cd test7
  81 clean
  82 select -assert-count 1 c:used
  83 select -assert-none c:* c:used %d