tests/various/src.ys

   1 logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
   2 logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
   3 read_verilog <<EOT
   4 module top(input i, output o, p);
   5 always @* o <= i;
   6 always @* p = i;
   7 endmodule
   8 EOT