2 module test(input [7:0] a, b, c, d, output [7:0] x, y, z);
3 assign x = a + b, y = b + c, z = c + d;
10 submod -name mycell gate/x %ci*
11 design -copy-to mymap mycell
12 extract -map %mymap gate
14 select -assert-count 3 gold/t:*
15 select -assert-count 3 gold/t:$add
17 select -assert-count 3 gate/t:*
18 select -assert-count 3 gate/t:mycell
20 miter -equiv -flatten gold gate miter
21 sat -verify -prove trigger 0 miter