Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
[yosys.git] / tests / various / sv_defines_too_few.ys
1 # Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
2 # arguments actually passes 1 empty argument).
3 logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
4 read_verilog <<EOT
5 `define foo(x=1, y)
6 `foo()
7 EOT