tests/various/sv_implicit_ports.sh

   1 #!/bin/bash
   2
   3 trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
   4
   5 # Simple case
   6 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
   7 module add(input [7:0] a, input [7:0] b, output [7:0] q);
   8         assign q = a + b;
   9 endmodule
  10
  11 module top(input [7:0] a, output [7:0] q);
  12         wire [7:0] b = 8'd42;
  13         add add_i(.*);
  14 endmodule
  15 EOT
  16
  17 # Generate block
  18 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
  19 module add(input [7:0] a, input [7:0] b, output [7:0] q);
  20 assign q = a + b;
  21 endmodule
  22
  23 module top(input [7:0] a, output [7:0] q);
  24         generate
  25         if (1) begin:ablock
  26                 wire [7:0] b = 8'd42;
  27                 add add_i(.*);
  28         end
  29         endgenerate
  30 endmodule
  31 EOT
  32
  33 # Missing wire
  34 ((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
  35 module add(input [7:0] a, input [7:0] b, output [7:0] q);
  36         assign q = a + b;
  37 endmodule
  38
  39 module top(input [7:0] a, output [7:0] q);
  40         add add_i(.*);
  41 endmodule
  42 EOT
  43 ) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
  44
  45 # Incorrectly sized wire
  46 ((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
  47 module add(input [7:0] a, input [7:0] b, output [7:0] q);
  48         assign q = a + b;
  49 endmodule
  50
  51 module top(input [7:0] a, output [7:0] q);
  52         wire [6:0] b = 6'd42;
  53         add add_i(.*);
  54 endmodule
  55 EOT
  56 ) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
  57
  58 # Defaults
  59 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
  60 module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
  61 assign q = a + b;
  62 endmodule
  63
  64 module top(input [7:0] a, output [7:0] q);
  65         add add_i(.*);
  66 endmodule
  67 EOT
  68
  69 # Parameterised module
  70 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
  71 module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
  72 assign q = a + b;
  73 endmodule
  74
  75 module top(input [7:0] a, output [7:0] q);
  76         add #(.N(8)) add_i(.*);
  77 endmodule
  78 EOT
  79
  80 # Parameterised blackbox module
  81 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
  82 (* blackbox *)
  83 module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
  84 endmodule
  85
  86 module top(input [7:0] a, b, output [7:0] q);
  87         add #(.N(8)) add_i(.*);
  88 endmodule
  89 EOT
  90
  91 # Parameterised blackbox module - incorrect width
  92 ((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
  93 (* blackbox *)
  94 module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
  95 endmodule
  96
  97 module top(input [7:0] a, b, output [7:0] q);
  98         add #(.N(6)) add_i(.*);
  99 endmodule
 100 EOT
 101 ) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
 102
 103 # Mixed implicit and explicit 1
 104 ../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
 105 module add(input [7:0] a, input [7:0] b, output [7:0] q);
 106         assign q = a + b;
 107 endmodule
 108
 109 module top(input [7:0] a, output [7:0] q);
 110         add add_i(.b(8'd42), .*);
 111 endmodule
 112 EOT
 113
 114 # Mixed implicit and explicit 2
 115 (../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
 116 module add(input [7:0] a, input [7:0] b, output [7:0] q);
 117         assign q = a + b;
 118 endmodule
 119
 120 module top(input [7:0] a, input [9:0] b, output [7:0] q);
 121         add add_i(.b, .*);
 122 endmodule
 123 EOT
 124 ) 2>&1 | grep -F "Warning: Resizing cell port top.add_i.b from 10 bits to 8 bits." > /dev/null