2 module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
3 assign o = (j >> 4) - i;
14 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
18 design -import gold -as gold
19 design -import gate -as gate
21 miter -equiv -flatten -make_assert -make_outputs gold gate miter
22 sat -verify -prove-asserts -show-ports miter
27 module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
28 assign o = (j >>> 4) - i;
39 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
43 design -import gold -as gold
44 design -import gate -as gate
46 miter -equiv -flatten -make_assert -make_outputs gold gate miter
47 sat -verify -prove-asserts -show-ports miter
51 # Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
65 assign b = b_reg[1:0];
66 always @(posedge clk or posedge rst) begin
79 select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i