tests/various/wreduce.ys

   1 read_verilog <<EOT
   2 module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
   3     assign o = (j >> 4) - i;
   4 endmodule
   5 EOT
   6
   7 hierarchy -auto-top
   8 proc
   9 design -save gold
  10
  11 opt_expr
  12 wreduce
  13
  14 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
  15
  16 design -stash gate
  17
  18 design -import gold -as gold
  19 design -import gate -as gate
  20
  21 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  22 sat -verify -prove-asserts -show-ports miter
  23
  24 ##########
  25
  26 read_verilog <<EOT
  27 module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
  28     assign o = (j >>> 4) - i;
  29 endmodule
  30 EOT
  31
  32 hierarchy -auto-top
  33 proc
  34 design -save gold
  35
  36 opt_expr
  37 wreduce
  38
  39 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
  40
  41 design -stash gate
  42
  43 design -import gold -as gold
  44 design -import gate -as gate
  45
  46 miter -equiv -flatten -make_assert -make_outputs gold gate miter
  47 sat -verify -prove-asserts -show-ports miter
  48
  49 ##########
  50
  51 # Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
  52 design -reset
  53 read_verilog <<EOT
  54 module top(
  55     input clk,
  56     input rst,
  57     input [2:0] a,
  58     output [1:0] b
  59 );
  60     reg [2:0] b_reg;
  61     initial begin
  62         b_reg <= 3'b0;
  63     end
  64
  65     assign b = b_reg[1:0];
  66     always @(posedge clk or posedge rst) begin
  67         if(rst) begin
  68             b_reg <= 3'b0;
  69         end else begin
  70             b_reg <= a;
  71         end
  72     end
  73 endmodule
  74 EOT
  75
  76 proc
  77 wreduce
  78
  79 select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i