tests/various/write_gzip.ys

   1 read_verilog <<EOT
   2 module top(input a, output y);
   3 assign y = !a;
   4 endmodule
   5 EOT
   6
   7 prep -top top
   8 write_verilog write_gzip.v.gz
   9 design -reset
  10
  11 ! rm -f write_gzip.v
  12 ! gunzip write_gzip.v.gz
  13 read_verilog write_gzip.v
  14 ! rm -f write_gzip.v
  15 hierarchy -top top
  16 select -assert-any top