tests/various/xaiger.ys

   1 read_verilog <<EOT
   2 module top(input a, b, output c);
   3 bb #(1) bb();
   4 endmodule
   5
   6 module bb(input a, b, output c);
   7 parameter p = 0;
   8 assign c = a ^ b;
   9 endmodule
  10 EOT
  11 blackbox bb
  12 hierarchy
  13 write_xaiger /dev/null