tests/verilog/block_labels.ys

   1 read_verilog <<EOT
   2 module foo;
   3
   4         genvar a = 0;
   5         for (a = 0; a < 10; a++) begin : a
   6         end : a
   7 endmodule
   8 EOT
   9 read_verilog <<EOT
  10 module foo2;
  11
  12         genvar a = 0;
  13         for (a = 0; a < 10; a++) begin : a
  14         end
  15 endmodule
  16 EOT
  17
  18 logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
  19 read_verilog <<EOT
  20 module foo3;
  21
  22         genvar a = 0;
  23         for (a = 0; a < 10; a++) begin : a
  24         end : b
  25 endmodule
  26 EOT