tests/verilog/conflict_wire_memory.ys

   1 logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
   2 read_verilog <<EOT
   3 module top;
   4     reg [2:0] x [0:0];
   5     reg [2:0] x;
   6 endmodule
   7 EOT