tests/verilog/delay_risefall.ys

   1 logger -expect-no-warnings
   2 read_verilog <<EOT
   3 module test (a, b, c, y);
   4     input a;
   5     input signed [1:0] b;
   6     input signed [2:0] c;
   7     output y;
   8     assign #(12.5, 14.5) y = ^(a ? b : c);
   9 endmodule
  10 EOT
  11
  12 design -reset
  13 logger -expect-no-warnings
  14 read_verilog << EOT
  15 module test (input [7:0] a, b, c, d, output [7:0] x, y, z);
  16     assign #(20, 20, 25) x = a + b, y = b + c, z = c + d;
  17 endmodule
  18 EOT
  19
  20 design -reset
  21 logger -expect-no-warnings
  22 read_verilog <<EOT
  23 module test (a, b, c, y);
  24     localparam TIME_STEP = 0.011;
  25     input signed [3:0] a;
  26     input signed [1:0] b;
  27     input signed [1:0] c;
  28     output [5:0] y;
  29     assign #(TIME_STEP, TIME_STEP, TIME_STEP) y = (a >> b) >>> c;
  30 endmodule
  31 EOT
  32
  33 design -reset
  34 logger -expect-no-warnings
  35 read_verilog <<EOT
  36 module test;
  37     localparam TIME_STEP = 0.7;
  38     wire o, a, b;
  39     and #(TIME_STEP, 2) and_gate (o, a, b);
  40     wire #(0, TIME_STEP, TIME_STEP) x;
  41     assign o = x;
  42 endmodule
  43 EOT
  44
  45 design -reset
  46 logger -expect warning "Yosys has only limited support for tri-state logic at the moment." 1
  47 read_verilog <<EOT
  48 module test (input en, input a, input b, output c);
  49     wire [15:0] add0_res = a + b;
  50     assign #(3, 3) c = (en) ? a : 1'bz;
  51 endmodule
  52 EOT
  53
  54 design -reset
  55 logger -expect-no-warnings
  56 read_verilog <<EOT
  57 module test (input en, d, t_rise, t_fall);
  58     reg o;
  59     always @*
  60         if (en)
  61             o = #(t_rise, t_fall, 50) ~d;
  62 endmodule
  63 EOT
  64
  65 design -reset
  66 logger -expect-no-warnings
  67 read_verilog <<EOT
  68 module test #(parameter DELAY_RISE = 0, DELAY_FALL = 0, DELAY_Z = 0)
  69             (input clock, input reset, input req_0, input req_1, output gnt_0, output gnt_1);
  70     parameter SIZE = 3;
  71     parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100;
  72     reg [SIZE-1:0] state;
  73     reg [SIZE-1:0] next_state;
  74     reg gnt_0, gnt_1;
  75
  76     always @ (state or req_0 or req_1)
  77     begin : FSM_COMBO
  78         next_state = 3'b000;
  79         case (state)
  80         IDLE : if (req_0 == 1'b1) begin
  81                     next_state = #(DELAY_RISE * 2) GNT0;
  82                 end else if (req_1 == 1'b1) begin
  83                     next_state = #(DELAY_RISE * 2.5, DELAY_FALL) GNT1;
  84                 end else begin
  85                     next_state = #(DELAY_RISE * 2.5, DELAY_FALL, DELAY_Z) IDLE;
  86                 end
  87         GNT0 : if (req_0 == 1'b1) begin
  88                     #(DELAY_RISE, DELAY_FALL) next_state = GNT0;
  89                 end else begin
  90                     #DELAY_RISE next_state = IDLE;
  91                 end
  92         GNT1 : if (req_1 == 1'b1) begin
  93                     #10 next_state = GNT1;
  94                 end else begin
  95                     #(10) next_state = IDLE;
  96                 end
  97         default : next_state = IDLE;
  98         endcase
  99     end
 100
 101     always @ (posedge clock)
 102     begin : FSM_SEQ
 103         if (reset == 1'b1) begin
 104             #3 state <= IDLE;
 105         end else begin
 106             #(1, 3) state <= next_state;
 107         end
 108     end
 109
 110     always @ (posedge clock)
 111     begin : FSM_OUTPUT
 112         if (reset == 1'b1) begin
 113             gnt_0 <= #(DELAY_RISE, DELAY_FALL, DELAY_Z) 1'b0;
 114             gnt_1 <= #1 1'b0;
 115         end else begin
 116             case (state)
 117             IDLE : begin
 118                         gnt_0 <= #(DELAY_RISE, DELAY_FALL, DELAY_Z) 1'b0;
 119                         gnt_1 <= #1 1'b0;
 120                     end
 121             GNT0 : begin
 122                         gnt_0 <= #(DELAY_RISE, DELAY_FALL) 1'b1;
 123                         gnt_1 <= #1 1'b0;
 124                     end
 125             GNT1 : begin
 126                         gnt_0 <= #(DELAY_RISE) 1'b0;
 127                         gnt_1 <= #1 1'b1;
 128                     end
 129             default : begin
 130                         gnt_0 <= 1'b0;
 131                         gnt_1 <= 1'b0;
 132                     end
 133             endcase
 134         end
 135     end
 136 endmodule
 137 EOT
 138
 139 design -reset
 140 logger -expect-no-warnings
 141 read_verilog <<EOT
 142 module test;
 143     reg q;
 144     initial #(1,2) q = 1;
 145 endmodule
 146 EOT
 147
 148 design -reset
 149 logger -expect-no-warnings
 150 read_verilog <<EOT
 151 module test #(parameter hyst = 16)
 152             (input [0:1] inA, input rst, output reg out);
 153     parameter real updatePeriod = 100.0;
 154     initial out = 1'b0;
 155     always #updatePeriod begin
 156         if (rst) out <= 1'b0;
 157         else if (inA[0] > inA[1]) out <= 1'b1;
 158         else if (inA[0] < inA[1] - hyst) out <= 1'b0;
 159     end
 160 endmodule
 161 EOT
 162
 163 design -reset
 164 logger -expect-no-warnings
 165 read_verilog <<EOT
 166 module test #(parameter hyst = 16)
 167             (input [0:1] inA, input rst, output reg out);
 168     parameter updatePeriod = (100:125:200);
 169     initial out = 1'b0;
 170     always #updatePeriod begin
 171         if (rst) out <= 1'b0;
 172         else if (inA[0] > inA[1]) out <= 1'b1;
 173         else if (inA[0] < inA[1] - hyst) out <= 1'b0;
 174     end
 175 endmodule
 176 EOT
 177
 178 design -reset
 179 logger -expect-no-warnings
 180 read_verilog <<EOT
 181 module test;
 182     reg clk;
 183     initial clk = 1'b0;
 184     always #(100, 180, 230) clk = ~clk;
 185 endmodule
 186 EOT
 187
 188 design -reset
 189 logger -expect-no-warnings
 190 read_verilog <<EOT
 191 module test;
 192     reg clk;
 193     initial clk = 1'b0;
 194     always clk = #(100, 180, 230) ~clk;
 195     task t_test;
 196         sig_036_A <= #(2, 4, 5.5) 0;
 197         sig_036_B <= #(1.3, 3) 0;
 198         sig_036_S <= #(2) 0;
 199         #(100, 200, 300);
 200         sig_036_A <= #(2 : 3 : 5) ~0;
 201         sig_036_B <= #(4 : 6 : 6, 10) ~0;
 202         sig_036_S <= #(1 : 2 : 3, 2 : 2 : 3, 10) ~0;
 203         #100;
 204     endtask
 205 endmodule
 206 EOT
 207
 208 design -reset
 209 logger -expect-no-warnings
 210 read_verilog <<EOT
 211 module test (clk, en, i, o);
 212     input clk, en, i;
 213     reg p;
 214     output o;
 215     always @ (posedge clk)
 216     begin
 217         if (en) begin
 218             p <= #(5:15:25, 20, 30) i;
 219         end else begin
 220             #(5, 3:5:8, 10) p <= i;
 221         end
 222     end
 223     assign #(10, 20, 15:20:30) o = p;
 224 endmodule
 225 EOT