tests/xilinx/mul_unsigned.v

   1 /*
   2 Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
   3 */
   4
   5 // Unsigned 16x24-bit Multiplier
   6 // 1 latency stage on operands
   7 // 3 latency stage after the multiplication
   8 // File: multipliers2.v
   9 //
  10 module mul_unsigned (clk, A, B, RES);
  11 parameter WIDTHA = /*16*/ 6;
  12 parameter WIDTHB = /*24*/ 9;
  13 input clk;
  14 input [WIDTHA-1:0] A;
  15 input [WIDTHB-1:0] B;
  16 output [WIDTHA+WIDTHB-1:0] RES;
  17 reg [WIDTHA-1:0] rA;
  18 reg [WIDTHB-1:0] rB;
  19 reg [WIDTHA+WIDTHB-1:0] M [3:0];
  20 integer i;
  21 always @(posedge clk)
  22  begin
  23  rA <= A;
  24  rB <= B;
  25  M[0] <= rA * rB;
  26  for (i = 0; i < 3; i = i+1)
  27  M[i+1] <= M[i];
  28  end
  29 assign RES = M[3];
  30 endmodule