Fixed vivado related xsthammer bugs
[yosys.git] / tests / xsthammer / report.sh
1 #!/bin/bash
2
3 if [ $# -eq 0 ]; then
4 echo "Usage: $0 <job_id>" >&2
5 exit 1
6 fi
7
8 job="$1"
9 set --
10
11 set -ex
12 rm -rf report_temp/$job
13 mkdir -p report report_temp/$job
14 cd report_temp/$job
15
16 cp ../../vivado/$job.v syn_vivado.v
17 cp ../../quartus/$job.v syn_quartus.v
18 cp ../../xst/$job.v syn_xst.v
19 cp ../../rtl/$job.v rtl.v
20
21 yosys -p 'hierarchy; proc; opt; techmap; abc; opt' -b 'verilog -noattr' -o syn_yosys.v ../../rtl/$job.v
22 cat ../../xl_cells.v ../../cy_cells.v > cells.v
23
24 {
25 echo "module ${job}_test(a, b, y1, y2);"
26 sed -r '/^(input|output) / !d; /output/ { s/ y;/ y1;/; p; }; s/ y1;/ y2;/;' rtl.v
27 echo "${job}_1 uut1 (.a(a), .b(b), .y(y1));"
28 echo "${job}_2 uut2 (.a(a), .b(b), .y(y2));"
29 echo "endmodule"
30 } > test.v
31
32 echo -n > fail_patterns.txt
33 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
34 for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
35 if test -f result.${q}.${p}.txt; then
36 cp result.${q}.${p}.txt result.${p}.${q}.txt
37 continue
38 fi
39
40 {
41 echo "read_verilog -DGLBL $p.v"
42 echo "rename $job ${job}_1"
43
44 echo "read_verilog -DGLBL $q.v"
45 echo "rename $job ${job}_2"
46
47 echo "read_verilog cells.v test.v"
48 echo "hierarchy -top ${job}_test"
49 echo "proc; opt; flatten ${job}_test"
50 echo "hierarchy -check -top ${job}_test"
51
52 echo "! touch test.$p.$q.input_ok"
53 echo "sat -timeout 10 -verify-no-timeout -show a,b,y1,y2 -prove y1 y2 ${job}_test"
54 } > test.$p.$q.ys
55
56 if yosys -l test.$p.$q.log test.$p.$q.ys; then
57 if grep TIMEOUT test.$p.$q.log; then
58 echo TIMEOUT > result.${p}.${q}.txt
59 else
60 echo PASS > result.${p}.${q}.txt
61 fi
62 else
63 echo $( grep '^ *\\[ab] ' test.$p.$q.log | gawk '{ print $4; }' | tr -d '\n' ) >> fail_patterns.txt
64 echo FAIL > result.${p}.${q}.txt
65 fi
66
67 # this fails if an error was encountered before the 'sat' command
68 rm test.$p.$q.input_ok
69 done; done
70
71 {
72 echo "module testbench;"
73
74 sed -r '/^input / !d; s/^input/reg/;' rtl.v
75 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
76 sed -r "/^output / !d; s/^output/wire/; s/ y;/ ${p}_y;/;" rtl.v
77 echo "${job}_${p} uut_${p} (.a(a), .b(b), .y(${p}_y));"
78 done
79
80 echo "initial begin"
81 extra_patterns=""
82 bits=$( echo $( grep '^input' rtl.v | cut -f2 -d'[' | cut -f1 -d: | tr '\n' '+' )2 | bc; )
83 for x in 1 2 3 4 5 6 7 8 9 0; do
84 extra_patterns="$extra_patterns $( echo $job$x | sha1sum | gawk "{ print \"160'h\" \$1; }" )"
85 done
86 for pattern in $bits\'b0 ~$bits\'b0 $( sed "s/^/$bits'b/;" < fail_patterns.txt ) $extra_patterns; do
87 echo " { a, b } <= $pattern; #1;"
88 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
89 echo " \$display(\"++RPT++ %b $p\", ${p}_y);"
90 done
91 echo " \$display(\"++RPT++ ----\");"
92 done
93 echo "end"
94
95 echo "endmodule"
96
97 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
98 sed "s/^module ${job}/module ${job}_${p}/; /^\`timescale/ d;" < $p.v
99 done
100
101 cat cells.v
102 } > testbench.v
103
104 /opt/altera/13.0/modelsim_ase/bin/vlib work
105 /opt/altera/13.0/modelsim_ase/bin/vlog testbench.v
106 /opt/altera/13.0/modelsim_ase/bin/vsim -c -do "run; exit" work.testbench | tee sim_modelsim.log
107
108 . /opt/Xilinx/14.5/ISE_DS/settings64.sh
109 vlogcomp testbench.v
110 fuse -o testbench testbench
111 { echo "run all"; echo "exit"; } > run-all.tcl
112 ./testbench -tclbatch run-all.tcl | tee sim_isim.log
113
114 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
115 for q in isim modelsim; do
116 echo $( grep '++RPT++' sim_$q.log | sed 's,.*++RPT++ ,,' | grep " $p\$" | gawk '{ print $1; }' | md5sum | gawk '{ print $1; }' ) > result.${p}.${q}.txt
117 done; done
118
119 echo "#00ff00" > color_PASS.txt
120 echo "#ff0000" > color_FAIL.txt
121
122 if cmp result.rtl.isim.txt result.rtl.modelsim.txt; then
123 echo "#00ff00" > color_$( cat result.rtl.isim.txt ).txt
124 else
125 echo "#00ff00" > color_NO_SIM_COMMON.txt
126 fi
127
128 {
129 echo "<h3>Hammer Report: $job</h3>"
130 echo "<table border>"
131 echo "<tr><th width=\"100\"></th>"
132 for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
133 echo "<th width=\"100\">$q</th>"
134 done
135 echo "</tr>"
136 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
137 echo "<tr><th>$p</th>"
138 for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
139 read result < result.${p}.${q}.txt
140 if ! test -f color_$result.txt; then
141 case $( ls color_*.txt | wc -l ) in
142 3) echo "#ffff00" > color_$result.txt ;;
143 4) echo "#ff00ff" > color_$result.txt ;;
144 5) echo "#00ffff" > color_$result.txt ;;
145 *) echo "#888888" > color_$result.txt ;;
146 esac
147 fi
148 echo "<td align=\"center\" bgcolor=\"$( cat color_$result.txt )\">$( echo $result | cut -c1-8 )</td>"
149 done
150 echo "</tr>"
151 done
152 echo "<tr><td colspan=\"8\"><pre>$( perl -pe 's/([<>&])/"&#".ord($1).";"/eg;' rtl.v |
153 perl -pe 's!([^\w#]|^)(\w+)\b!$x = $1; $y = $2; sprintf("%s<span style=\"color: %s;\">%s</span>", $x, $y =~ /module|input|wire|output|assign|signed|endmodule/ ? "#008800;" : "#000088;", $y)!eg' )</pre></td></tr>"
154 #perl -pe 's,\b(module|input|wire|output|assign|signed|endmodule)\b,<span style="color: #008800;">$1</span>,g' )</pre></td></tr>"
155 echo "</table>"
156 } > ../../report/$job.html
157
158 sync
159 echo READY.
160