tests/xsthammer/xl_cells.v

   1
   2 module IBUF(O, I);
   3 output O;
   4 input  I;
   5 assign O = I;
   6 endmodule
   7
   8 module OBUF(O, I);
   9 output O;
  10 input  I;
  11 assign O = I;
  12 endmodule
  13
  14 module GND(G);
  15 output G;
  16 assign G = 0;
  17 endmodule
  18
  19 module INV(O, I);
  20 input I;
  21 output O;
  22 assign O = !I;
  23 endmodule
  24
  25 module LUT1(O, I0);
  26 parameter INIT = 0;
  27 input I0;
  28 wire [1:0] lutdata = INIT;
  29 wire [0:0] idx = { I0 };
  30 output O;
  31 assign O = lutdata[idx];
  32 endmodule
  33
  34 module LUT2(O, I0, I1);
  35 parameter INIT = 0;
  36 input I0, I1;
  37 wire [3:0] lutdata = INIT;
  38 wire [1:0] idx = { I1, I0 };
  39 output O;
  40 assign O = lutdata[idx];
  41 endmodule
  42
  43 module LUT3(O, I0, I1, I2);
  44 parameter INIT = 0;
  45 input I0, I1, I2;
  46 wire [7:0] lutdata = INIT;
  47 wire [2:0] idx = { I2, I1, I0 };
  48 output O;
  49 assign O = lutdata[idx];
  50 endmodule
  51
  52 module LUT4(O, I0, I1, I2, I3);
  53 parameter INIT = 0;
  54 input I0, I1, I2, I3;
  55 wire [15:0] lutdata = INIT;
  56 wire [3:0] idx = { I3, I2, I1, I0 };
  57 output O;
  58 assign O = lutdata[idx];
  59 endmodule
  60
  61 module LUT5(O, I0, I1, I2, I3, I4);
  62 parameter INIT = 0;
  63 input I0, I1, I2, I3, I4;
  64 wire [31:0] lutdata = INIT;
  65 wire [4:0] idx = { I4, I3, I2, I1, I0 };
  66 output O;
  67 assign O = lutdata[idx];
  68 endmodule
  69
  70 module LUT6(O, I0, I1, I2, I3, I4, I5);
  71 parameter INIT = 0;
  72 input I0, I1, I2, I3, I4, I5;
  73 wire [63:0] lutdata = INIT;
  74 wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
  75 output O;
  76 assign O = lutdata[idx];
  77 endmodule
  78
  79 module MUXCY(O, CI, DI, S);
  80 input CI, DI, S;
  81 output O;
  82 assign O = S ? CI : DI;
  83 endmodule
  84
  85 module MUXF7(O, I0, I1, S);
  86 input I0, I1, S;
  87 output O;
  88 assign O = S ? I1 : I0;
  89 endmodule
  90
  91 module MUXF8(O, I0, I1, S);
  92 input I0, I1, S;
  93 output O;
  94 assign O = S ? I1 : I0;
  95 endmodule
  96
  97 module VCC(P);
  98 output P;
  99 assign P = 1;
 100 endmodule
 101
 102 module XORCY(O, CI, LI);
 103 input CI, LI;
 104 output O;
 105 assign O = CI ^ LI;
 106 endmodule
 107
 108 module CARRY4(CO, O, CI, CYINIT, DI, S);
 109 output [3:0] CO, O;
 110 input  CI, CYINIT;
 111 input  [3:0] DI, S;
 112 wire ci_or_cyinit;
 113 assign O = S ^ {CO[2:0], ci_or_cyinit};
 114 assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
 115 assign CO[1] = S[1] ? CO[0] : DI[1];
 116 assign CO[2] = S[2] ? CO[1] : DI[2];
 117 assign CO[3] = S[3] ? CO[2] : DI[3];
 118 assign ci_or_cyinit = CI | CYINIT;
 119 endmodule
 120