Progress on xsthammer
[yosys.git] / tests / xsthammer / xl_cells_tb.v
1
2 module TB_GND(ok);
3 wire MY_G, XL_G;
4 MY_GND MY(.G(MY_G));
5 XL_GND XL(.G(XL_G));
6 output ok = MY_G == XL_G;
7 endmodule
8
9 module TB_INV(ok, I);
10 input I;
11 wire MY_O, XL_O;
12 MY_INV MY(.O(MY_O), .I(I));
13 XL_INV XL(.O(XL_O), .I(I));
14 output ok = MY_O == XL_O;
15 endmodule
16
17 module TB_LUT2(ok, I0, I1);
18 input I0, I1;
19 wire MY_O, XL_O;
20 MY_LUT2 #(.INIT(1234567)) MY(.O(MY_O), .I0(I0), .I1(I1));
21 XL_LUT2 #(.INIT(1234567)) XL(.O(XL_O), .I0(I0), .I1(I1));
22 output ok = MY_O == XL_O;
23 endmodule
24
25 module TB_LUT3(ok, I0, I1, I2);
26 input I0, I1, I2;
27 wire MY_O, XL_O;
28 MY_LUT3 #(.INIT(1234567)) MY(.O(MY_O), .I0(I0), .I1(I1), .I2(I2));
29 XL_LUT3 #(.INIT(1234567)) XL(.O(XL_O), .I0(I0), .I1(I1), .I2(I2));
30 output ok = MY_O == XL_O;
31 endmodule
32
33 module TB_LUT4(ok, I0, I1, I2, I3);
34 input I0, I1, I2, I3;
35 wire MY_O, XL_O;
36 MY_LUT4 #(.INIT(1234567)) MY(.O(MY_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
37 XL_LUT4 #(.INIT(1234567)) XL(.O(XL_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
38 output ok = MY_O == XL_O;
39 endmodule
40
41 module TB_LUT5(ok, I0, I1, I2, I3, I4);
42 input I0, I1, I2, I3, I4;
43 wire MY_O, XL_O;
44 MY_LUT5 #(.INIT(1234567)) MY(.O(MY_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
45 XL_LUT5 #(.INIT(1234567)) XL(.O(XL_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
46 output ok = MY_O == XL_O;
47 endmodule
48
49 module TB_LUT6(ok, I0, I1, I2, I3, I4, I5);
50 input I0, I1, I2, I3, I4, I5;
51 wire MY_O, XL_O;
52 MY_LUT6 #(.INIT(1234567)) MY(.O(MY_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
53 XL_LUT6 #(.INIT(1234567)) XL(.O(XL_O), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
54 output ok = MY_O == XL_O;
55 endmodule
56
57 module TB_MUXCY(ok, CI, DI, S);
58 input CI, DI, S;
59 wire MY_O, XL_O;
60 MY_MUXCY MY(.O(MY_O), .CI(CI), .DI(DI), .S(S));
61 XL_MUXCY XL(.O(XL_O), .CI(CI), .DI(DI), .S(S));
62 output ok = MY_O == XL_O;
63 endmodule
64
65 module TB_MUXF7(ok, I0, I1, S);
66 input I0, I1, S;
67 wire MY_O, XL_O;
68 MY_MUXF7 MY(.O(MY_O), .I0(I0), .I1(I1), .S(S));
69 XL_MUXF7 XL(.O(XL_O), .I0(I0), .I1(I1), .S(S));
70 output ok = MY_O == XL_O;
71 endmodule
72
73 module TB_VCC(ok);
74 wire MY_P, XL_P;
75 MY_VCC MY(.P(MY_P));
76 XL_VCC XL(.P(XL_P));
77 output ok = MY_P == XL_P;
78 endmodule
79
80 module TB_XORCY(ok, CI, LI);
81 input CI, LI;
82 wire MY_O, XL_O;
83 MY_XORCY MY(.O(MY_O), .CI(CI), .LI(LI));
84 XL_XORCY XL(.O(XL_O), .CI(CI), .LI(LI));
85 output ok = MY_O == XL_O;
86 endmodule
87