top.py

   1 from fractions import Fraction
   2 from math import ceil
   3 from operator import itemgetter
   4 from collections import defaultdict
   5
   6 from migen.fhdl.std import *
   7 from migen.bus import wishbone, csr, lasmibus, dfi
   8 from migen.bus import wishbone2lasmi, wishbone2csr
   9 from migen.bank import csrgen
  10 from mibuild.generic_platform import ConstraintError
  11
  12 from misoclib import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
  13         identifier, timer, minimac3, framebuffer, dvisampler, gpio, memtest
  14
  15 clk_freq = (83 + Fraction(1, 3))*1000000
  16 sram_size = 4096 # in bytes
  17 l2_size = 8192 # in bytes
  18
  19 clk_period_ns = 1000000000/clk_freq
  20 def ns(t, margin=True):
  21         if margin:
  22                 t += clk_period_ns/2
  23         return ceil(t/clk_period_ns)
  24
  25 sdram_geom = lasmicon.GeomSettings(
  26         bank_a=2,
  27         row_a=13,
  28         col_a=10
  29 )
  30 sdram_timing = lasmicon.TimingSettings(
  31         tRP=ns(15),
  32         tRCD=ns(15),
  33         tWR=ns(15),
  34         tWTR=2,
  35         tREFI=ns(7800, False),
  36         tRFC=ns(70),
  37
  38         req_queue_size=8,
  39         read_time=32,
  40         write_time=16
  41 )
  42
  43 class MXClockPads:
  44         def __init__(self, platform):
  45                 self.clk50 = platform.request("clk50")
  46                 self.trigger_reset = 0
  47                 try:
  48                         self.trigger_reset = platform.request("user_btn", 1)
  49                 except ConstraintError:
  50                         pass
  51                 self.norflash_rst_n = platform.request("norflash_rst_n")
  52                 ddram_clock = platform.request("ddram_clock")
  53                 self.ddr_clk_p = ddram_clock.p
  54                 self.ddr_clk_n = ddram_clock.n
  55                 eth_clocks = platform.request("eth_clocks")
  56                 self.eth_phy_clk = eth_clocks.phy
  57                 self.eth_rx_clk = eth_clocks.rx
  58                 self.eth_tx_clk = eth_clocks.tx
  59
  60 class SoC(Module):
  61         csr_base = 0xe0000000
  62         csr_map = {
  63                 "crg":                                  0,
  64                 "uart":                                 1,
  65                 "dfii":                                 2,
  66                 "identifier":                   3,
  67                 "timer0":                               4,
  68                 "minimac":                              5,
  69                 "fb":                                   6,
  70                 "lasmicon":                             7,
  71                 "dvisampler0":                  8,
  72                 "dvisampler0_edid_mem": 9,
  73                 "dvisampler1":                  10,
  74                 "dvisampler1_edid_mem": 11,
  75                 "pots":                                 12,
  76                 "buttons":                              13,
  77                 "leds":                                 14,
  78                 "memtest_w":                    15,
  79                 "memtest_r":                    16
  80         }
  81         interrupt_map = {
  82                 "uart":                 0,
  83                 "timer0":               1,
  84                 "minimac":              2,
  85                 "dvisampler0":  3,
  86                 "dvisampler1":  4,
  87         }
  88         known_platform_id = defaultdict(lambda: 0x554E, {
  89                 "mixxeo":       0x4D58,
  90                 "m1":           0x4D31
  91         })
  92
  93         def __init__(self, platform, platform_name, with_memtest):
  94                 #
  95                 # DFI
  96                 #
  97                 self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
  98                 self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
  99                         self.ddrphy.phy_settings.dfi_d, self.ddrphy.phy_settings.nphases)
 100                 self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
 101
 102                 #
 103                 # LASMI
 104                 #
 105                 self.submodules.lasmicon = lasmicon.LASMIcon(self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 106                 self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
 107
 108                 n_lasmims = 1 # wishbone bridging
 109                 if platform_name == "mixxeo":
 110                         n_lasmims += 4 # framebuffer (2-channel mixing) + 2 DVI samplers
 111                 if platform_name == "m1":
 112                         n_lasmims += 1 # framebuffer (single channel)
 113                 if with_memtest:
 114                         n_lasmims += 2 # writer + reader
 115                 self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], n_lasmims, self.lasmicon.nrowbits)
 116
 117                 lasmims = list(self.lasmixbar.masters)
 118                 lasmim_wb = lasmims.pop()
 119                 if platform_name == "mixxeo":
 120                         lasmim_fb0, lasmim_fb1, lasmim_dvi0, lasmim_dvi1 = (lasmims.pop() for i in range(4))
 121                 if platform_name == "m1":
 122                         lasmim_fb = lasmims.pop()
 123                 if with_memtest:
 124                         lasmim_mtw, lasmim_mtr = lasmims.pop(), lasmims.pop()
 125                 assert(not lasmims)
 126
 127                 #
 128                 # WISHBONE
 129                 #
 130                 self.submodules.cpu = lm32.LM32()
 131                 self.submodules.norflash = norflash.NorFlash(platform.request("norflash"), 12)
 132                 self.submodules.sram = wishbone.SRAM(sram_size)
 133                 self.submodules.minimac = minimac3.MiniMAC(platform.request("eth"))
 134                 self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, lasmim_wb)
 135                 self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
 136
 137                 # norflash     0x00000000 (shadow @0x80000000)
 138                 # SRAM/debug   0x10000000 (shadow @0x90000000)
 139                 # USB          0x20000000 (shadow @0xa0000000)
 140                 # Ethernet     0x30000000 (shadow @0xb0000000)
 141                 # SDRAM        0x40000000 (shadow @0xc0000000)
 142                 # CSR bridge   0x60000000 (shadow @0xe0000000)
 143                 self.submodules.wishbonecon = wishbone.InterconnectShared(
 144                         [
 145                                 self.cpu.ibus,
 146                                 self.cpu.dbus
 147                         ], [
 148                                 (lambda a: a[26:29] == 0, self.norflash.bus),
 149                                 (lambda a: a[26:29] == 1, self.sram.bus),
 150                                 (lambda a: a[26:29] == 3, self.minimac.membus),
 151                                 (lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone),
 152                                 (lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
 153                         ],
 154                         register=True)
 155
 156                 #
 157                 # CSR
 158                 #
 159                 self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
 160                 self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
 161                 self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq),
 162                         log2_int(l2_size))
 163                 self.submodules.timer0 = timer.Timer()
 164                 if platform_name == "mixxeo":
 165                         self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
 166                         self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga_out"), platform.request("dvi_out"),
 167                                 lasmim_fb0, lasmim_fb1)
 168                         self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
 169                         self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
 170                 if platform_name == "m1":
 171                         self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
 172                         self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
 173                         self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), None, lasmim_fb)
 174                 if with_memtest:
 175                         self.submodules.memtest_w = memtest.MemtestWriter(lasmim_mtw)
 176                         self.submodules.memtest_r = memtest.MemtestReader(lasmim_mtr)
 177
 178                 self.submodules.csrbankarray = csrgen.BankArray(self,
 179                         lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
 180                 self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
 181
 182                 #
 183                 # Interrupts
 184                 #
 185                 for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
 186                         if hasattr(self, k):
 187                                 self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
 188
 189                 #
 190                 # Clocking
 191                 #
 192                 self.comb += [
 193                         self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 194                         self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
 195                 ]