top.py

   1 from fractions import Fraction
   2
   3 from migen.fhdl.structure import *
   4 from migen.fhdl import verilog, autofragment
   5 from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr, dfi
   6
   7 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii
   8 import constraints
   9
  10 MHz = 1000000
  11 clk_freq = (83 + Fraction(1, 3))*MHz
  12 sram_size = 4096 # in bytes
  13 l2_size = 8192 # in bytes
  14
  15 dfi_a = 13
  16 dfi_ba = 2
  17 dfi_d = 128 # TODO -> 64
  18
  19 def ddrphy_clocking(crg, phy):
  20         names = [
  21                 "clk2x_90",
  22                 "clk4x_wr_left",
  23                 "clk4x_wr_strb_left",
  24                 "clk4x_wr_right",
  25                 "clk4x_wr_strb_right",
  26                 "clk4x_rd_left",
  27                 "clk4x_rd_strb_left",
  28                 "clk4x_rd_right",
  29                 "clk4x_rd_strb_right",
  30         ]
  31         comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
  32         return Fragment(comb)
  33
  34 def get():
  35         #
  36         # ASMI
  37         #
  38         asmihub0 = asmibus.Hub(23, 128, 12) # TODO: get hub from memory controller
  39         asmiport_wb = asmihub0.get_port()
  40         asmihub0.finalize()
  41
  42         #
  43         # DFI
  44         #
  45         ddrphy0 = s6ddrphy.S6DDRPHY(1, dfi_a, dfi_ba, dfi_d)
  46         dfii0 = dfii.DFIInjector(2, dfi_a, dfi_ba, dfi_d, 1)
  47         dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  48
  49         #
  50         # WISHBONE
  51         #
  52         cpu0 = lm32.LM32()
  53         norflash0 = norflash.NorFlash(25, 12)
  54         sram0 = sram.SRAM(sram_size//4)
  55         wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  56         wishbone2csr0 = wishbone2csr.WB2CSR()
  57
  58         # norflash     0x00000000 (shadow @0x80000000)
  59         # SRAM/debug   0x10000000 (shadow @0x90000000)
  60         # USB          0x20000000 (shadow @0xa0000000)
  61         # Ethernet     0x30000000 (shadow @0xb0000000)
  62         # SDRAM        0x40000000 (shadow @0xc0000000)
  63         # CSR bridge   0x60000000 (shadow @0xe0000000)
  64         wishbonecon0 = wishbone.InterconnectShared(
  65                 [
  66                         cpu0.ibus,
  67                         cpu0.dbus
  68                 ], [
  69                         (binc("000"), norflash0.bus),
  70                         (binc("001"), sram0.bus),
  71                         (binc("10"), wishbone2asmi0.wishbone),
  72                         (binc("11"), wishbone2csr0.wishbone)
  73                 ],
  74                 register=True,
  75                 offset=1)
  76
  77         #
  78         # CSR
  79         #
  80         uart0 = uart.UART(0, clk_freq, baud=115200)
  81         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
  82                 uart0.bank.interface,
  83                 ddrphy0.bank.interface,
  84                 dfii0.bank.interface
  85         ])
  86
  87         #
  88         # Interrupts
  89         #
  90         interrupts = Fragment([
  91                 cpu0.interrupt[0].eq(uart0.events.irq)
  92         ])
  93
  94         #
  95         # Housekeeping
  96         #
  97         crg0 = m1crg.M1CRG(50*MHz, clk_freq)
  98
  99         frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
 100         src_verilog, vns = verilog.convert(frag,
 101                 {crg0.trigger_reset},
 102                 name="soc",
 103                 clk_signal=crg0.sys_clk,
 104                 rst_signal=crg0.sys_rst,
 105                 return_ns=True)
 106         src_ucf = constraints.get(vns, crg0, norflash0, uart0, ddrphy0)
 107         return (src_verilog, src_ucf)