uart16550/uart_wb.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  uart_wb.v                                                   ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the "UART 16550 compatible" project    ////
   7 ////  http://www.opencores.org/cores/uart16550/                   ////
   8 ////                                                              ////
   9 ////  Documentation related to this project:                      ////
  10 ////  - http://www.opencores.org/cores/uart16550/                 ////
  11 ////                                                              ////
  12 ////  Projects compatibility:                                     ////
  13 ////  - WISHBONE                                                  ////
  14 ////  RS232 Protocol                                              ////
  15 ////  16550D uart (mostly supported)                              ////
  16 ////                                                              ////
  17 ////  Overview (main Features):                                   ////
  18 ////  UART core WISHBONE interface.                               ////
  19 ////                                                              ////
  20 ////  Known problems (limits):                                    ////
  21 ////  Inserts one wait state on all transfers.                    ////
  22 ////  Note affected signals and the way they are affected.        ////
  23 ////                                                              ////
  24 ////  To Do:                                                      ////
  25 ////  Nothing.                                                    ////
  26 ////                                                              ////
  27 ////  Author(s):                                                  ////
  28 ////      - gorban@opencores.org                                  ////
  29 ////      - Jacob Gorban                                          ////
  30 ////      - Igor Mohor (igorm@opencores.org)                      ////
  31 ////                                                              ////
  32 ////  Created:        2001/05/12                                  ////
  33 ////  Last Updated:   2001/05/17                                  ////
  34 ////                  (See log for the revision history)          ////
  35 ////                                                              ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 ////                                                              ////
  39 //// Copyright (C) 2000, 2001 Authors                             ////
  40 ////                                                              ////
  41 //// This source file may be used and distributed without         ////
  42 //// restriction provided that this copyright statement is not    ////
  43 //// removed from the file and that any derivative work contains  ////
  44 //// the original copyright notice and the associated disclaimer. ////
  45 ////                                                              ////
  46 //// This source file is free software; you can redistribute it   ////
  47 //// and/or modify it under the terms of the GNU Lesser General   ////
  48 //// Public License as published by the Free Software Foundation; ////
  49 //// either version 2.1 of the License, or (at your option) any   ////
  50 //// later version.                                               ////
  51 ////                                                              ////
  52 //// This source is distributed in the hope that it will be       ////
  53 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  54 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  55 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  56 //// details.                                                     ////
  57 ////                                                              ////
  58 //// You should have received a copy of the GNU Lesser General    ////
  59 //// Public License along with this source; if not, download it   ////
  60 //// from http://www.opencores.org/lgpl.shtml                     ////
  61 ////                                                              ////
  62 //////////////////////////////////////////////////////////////////////
  63 //
  64 // CVS Revision History
  65 //
  66 // $Log: not supported by cvs2svn $
  67 // Revision 1.16  2002/07/29 21:16:18  gorban
  68 // The uart_defines.v file is included again in sources.
  69 //
  70 // Revision 1.15  2002/07/22 23:02:23  gorban
  71 // Bug Fixes:
  72 //  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
  73 //   Problem reported by Kenny.Tung.
  74 //  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
  75 //
  76 // Improvements:
  77 //  * Made FIFO's as general inferrable memory where possible.
  78 //  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
  79 //  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
  80 //
  81 //  * Added optional baudrate output (baud_o).
  82 //  This is identical to BAUDOUT* signal on 16550 chip.
  83 //  It outputs 16xbit_clock_rate - the divided clock.
  84 //  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
  85 //
  86 // Revision 1.12  2001/12/19 08:03:34  mohor
  87 // Warnings cleared.
  88 //
  89 // Revision 1.11  2001/12/06 14:51:04  gorban
  90 // Bug in LSR[0] is fixed.
  91 // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
  92 //
  93 // Revision 1.10  2001/12/03 21:44:29  gorban
  94 // Updated specification documentation.
  95 // Added full 32-bit data bus interface, now as default.
  96 // Address is 5-bit wide in 32-bit data bus mode.
  97 // Added wb_sel_i input to the core. It's used in the 32-bit mode.
  98 // Added debug interface with two 32-bit read-only registers in 32-bit mode.
  99 // Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
 100 // My small test bench is modified to work with 32-bit mode.
 101 //
 102 // Revision 1.9  2001/10/20 09:58:40  gorban
 103 // Small synopsis fixes
 104 //
 105 // Revision 1.8  2001/08/24 21:01:12  mohor
 106 // Things connected to parity changed.
 107 // Clock devider changed.
 108 //
 109 // Revision 1.7  2001/08/23 16:05:05  mohor
 110 // Stop bit bug fixed.
 111 // Parity bug fixed.
 112 // WISHBONE read cycle bug fixed,
 113 // OE indicator (Overrun Error) bug fixed.
 114 // PE indicator (Parity Error) bug fixed.
 115 // Register read bug fixed.
 116 //
 117 // Revision 1.4  2001/05/31 20:08:01  gorban
 118 // FIFO changes and other corrections.
 119 //
 120 // Revision 1.3  2001/05/21 19:12:01  gorban
 121 // Corrected some Linter messages.
 122 //
 123 // Revision 1.2  2001/05/17 18:34:18  gorban
 124 // First 'stable' release. Should be sythesizable now. Also added new header.
 125 //
 126 // Revision 1.0  2001-05-17 21:27:13+02  jacob
 127 // Initial revision
 128 //
 129 //
 130
 131 // UART core WISHBONE interface
 132 //
 133 // Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
 134 // Company: Flextronics Semiconductor
 135 //
 136
 137 `include "uart_defines.v"
 138
 139 module uart_wb (clk, wb_rst_i,
 140         wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
 141         wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
 142         we_o, re_o // Write and read enable output for the core
 143 );
 144
 145 input             clk;
 146
 147 // WISHBONE interface
 148 input             wb_rst_i;
 149 input             wb_we_i;
 150 input             wb_stb_i;
 151 input             wb_cyc_i;
 152 input [3:0]   wb_sel_i;
 153 input [2:0]     wb_adr_i; //WISHBONE address line
 154
 155 input [7:0]  wb_dat_i; //input WISHBONE bus
 156 output [7:0] wb_dat_o;
 157 reg [7:0]        wb_dat_o;
 158 wire [7:0]       wb_dat_i;
 159 reg [7:0]        wb_dat_is;
 160
 161 output [2:0]    wb_adr_int; // internal signal for address bus
 162 input [7:0]   wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
 163 output [7:0]  wb_dat8_i;
 164 input [31:0]  wb_dat32_o; // 32 bit data output (for debug interface)
 165 output            wb_ack_o;
 166 output            we_o;
 167 output            re_o;
 168
 169 wire                      we_o;
 170 reg                       wb_ack_o;
 171 reg [7:0]         wb_dat8_i;
 172 wire [7:0]        wb_dat8_o;
 173 wire [2:0]      wb_adr_int; // internal signal for address bus
 174 reg [2:0]       wb_adr_is;
 175 reg                                                             wb_we_is;
 176 reg                                                             wb_cyc_is;
 177 reg                                                             wb_stb_is;
 178 wire [3:0]   wb_sel_i;
 179 reg                      wre ;// timing control signal for write or read enable
 180
 181 // wb_ack_o FSM
 182 reg [1:0]        wbstate;
 183 always  @(posedge clk or posedge wb_rst_i)
 184         if (wb_rst_i) begin
 185                 wb_ack_o <= 1'b0;
 186                 wbstate <= 0;
 187                 wre <= 1'b1;
 188         end else
 189                 case (wbstate)
 190                         0: begin
 191                                 if (wb_stb_is & wb_cyc_is) begin
 192                                         wre <= 0;
 193                                         wbstate <= 1;
 194                                         wb_ack_o <= 1;
 195                                 end else begin
 196                                         wre <= 1;
 197                                         wb_ack_o <= 0;
 198                                 end
 199                         end
 200                         1: begin
 201                            wb_ack_o <= 0;
 202                                 wbstate <= 2;
 203                                 wre <= 0;
 204                         end
 205                         2: begin
 206                                 wb_ack_o <= 0;
 207                                 wbstate <= 3;
 208                                 wre <= 0;
 209                         end
 210                         3: begin
 211                                 wb_ack_o <= 0;
 212                                 wbstate <= 0;
 213                                 wre <= 1;
 214                         end
 215                 endcase
 216
 217 assign we_o =  wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
 218 assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
 219
 220 // Sample input signals
 221 always  @(posedge clk or posedge wb_rst_i)
 222         if (wb_rst_i) begin
 223                 wb_adr_is <= 0;
 224                 wb_we_is <= 0;
 225                 wb_cyc_is <= 0;
 226                 wb_stb_is <= 0;
 227                 wb_dat_is <= 0;
 228         end else begin
 229                 wb_adr_is <= wb_adr_i;
 230                 wb_we_is <= wb_we_i;
 231                 wb_cyc_is <= wb_cyc_i;
 232                 wb_stb_is <= wb_stb_i;
 233                 wb_dat_is <= wb_dat_i;
 234         end
 235
 236 always @(posedge clk or posedge wb_rst_i)
 237         if (wb_rst_i)
 238                 wb_dat_o <= 0;
 239         else
 240                 wb_dat_o <= wb_dat8_o;
 241
 242 always @(wb_dat_is)
 243         wb_dat8_i = wb_dat_is;
 244
 245 assign wb_adr_int = wb_adr_is;
 246
 247
 248 endmodule
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