1 # Add the ARM CONTEXTIDR_EL2 miscreg.
3 if cpt
.get('root','isa') == 'arm':
4 for sec
in cpt
.sections():
6 # Search for all ISA sections
7 if re
.search('.*sys.*\.cpu.*\.isa$', sec
):
8 miscRegs
= cpt
.get(sec
, 'miscRegs').split()
9 # CONTEXTIDR_EL2 defaults to 0b11111100000000000001
10 miscRegs
[599:599] = [0xFC001]
11 cpt
.set(sec
, 'miscRegs', ' '.join(str(x
) for x
in miscRegs
))