util/cpt_upgraders/arm-sve.py

   1 def upgrader(cpt):
   2     """
   3     Update the checkpoint to support initial SVE implemtation.
   4     The updater is taking the following steps.
   5
   6     1) Set isa.haveSVE to false
   7     2) Set isa.sveVL to 1
   8     3) Add SVE misc registers in the checkpoint
   9     """
  10     if cpt.get('root','isa') == 'arm':
  11         for sec in cpt.sections():
  12             import re
  13             # Search for all ISA sections
  14             if re.search('.*sys.*\.cpu.*\.isa$', sec):
  15
  16                 # haveSVE = false
  17                 cpt.set(sec, 'haveSVE', 'false')
  18
  19                 # sveVL (sve Vector Length in quadword) = 1
  20                 # (This is a dummy value since haveSVE is set to false)
  21                 cpt.set(sec, 'sveVL', '1')
  22
  23                 # Updating SVE misc registers (dummy values)
  24                 mr = cpt.get(sec, 'miscRegs').split()
  25                 if len(mr) == 820:
  26                     print "MISCREG_SVE registers already seems to be inserted."
  27                 else:
  28                     # Replace MISCREG_FREESLOT_1 with MISCREG_ID_AA64ZFR0_EL1
  29                     mr[-1] = 0;
  30
  31                     mr.append(0); # Add dummy value for MISCREG_ZCR_EL3
  32                     mr.append(0); # Add dummy value for MISCREG_ZCR_EL2
  33                     mr.append(0); # Add dummy value for MISCREG_ZCR_EL12
  34                     mr.append(0); # Add dummy value for MISCREG_ZCR_EL1
  35                     cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
  36
  37 legacy_version = 15