util: Add a README file for the m5 utility.
[gem5.git] / util / cpt_upgraders / arm-sysreg-mapping-ns.py
1 # Copyright (c) 2016 ARM Limited
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35
36 # reflect updated register mappings for ARM ISA
37 def upgrader(cpt):
38 if cpt.get('root','isa') == 'arm':
39 for sec in cpt.sections():
40 import re
41 # Search for all ISA sections
42 if re.search('.*sys.*\.cpu.*\.isa\d*$', sec):
43 mr = cpt.get(sec, 'miscRegs').split()
44 if int(mr[0]) & 16 == 0: # CPSR reg width; 0 for AArch64
45 mr[112] = mr[111] # ACTLR_NS = ACTLR
46 mr[146] = mr[145] # ADFSR_NS = ADFSR
47 mr[149] = mr[148] # AIFSR_NS = AIFSR
48 mr[253] = mr[252] # AMAIR0_NS = AMAIR0
49 mr[289] = mr[288] # CNTP_CTL_NS = CNTP_CTL
50 mr[313] = mr[312] # CNTP_CVAL_NS = CNTP_CVAL
51 mr[286] = mr[285] # CNTP_TVAL_NS = CNTP_TVAL
52 mr[271] = mr[270] # CONTEXTIDR_NS = CONTEXTIDR
53 mr[104] = mr[103] # CSSELR_NS = CSSELR
54 mr[137] = mr[136] # DACR_NS = DACR
55 mr[155] = mr[154] # DFAR_NS = DFAR
56 mr[158] = mr[157] # IFAR_NS = IFAR
57 mr[143] = mr[142] # IFSR_NS = IFSR
58 mr[247] = mr[246] # NMRR_NS = NMRR
59 mr[166] = mr[165] # PAR_NS = PAR
60 mr[241] = mr[240] # PRRR_NS = PRRR
61 mr[ 4] = mr[424] # SPSR_SVC = SPSR_EL1
62 mr[ 7] = mr[435] # SPSR_HYP = SPSR_EL2
63 mr[ 5] = mr[442] # SPSR_MON = SPSR_EL3
64 mr[277] = mr[276] # TPIDRURO_NS = TPIDRURO
65 mr[280] = mr[279] # TPIDRPRW_NS = TPIDRPRW
66 mr[274] = mr[273] # TPIDRURW_NS = TPIDRURW
67 mr[132] = mr[131] # TTBCR_NS = TTBCR
68 mr[126] = mr[125] # TTBR0_NS = TTBR0
69 mr[129] = mr[128] # TTBR1_NS = TTBR1
70 mr[263] = mr[262] # VBAR_NS = VBAR
71
72 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))