1 # The ISA is now a separate SimObject, which means that we serialize
2 # it in a separate section instead of as a part of the ThreadContext.
4 isa
= cpt
.get('root','isa')
6 "alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ),
7 "arm" : ( "miscRegs" ),
8 "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
9 "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",
10 "tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
11 "htstate", "hintp", "htba", "hstick_cmpr",
12 "strandStatusReg", "fsr", "priContext", "secContext",
13 "partId", "lsuCtrlReg", "scratchPad",
14 "cpu_mondo_head", "cpu_mondo_tail",
15 "dev_mondo_head", "dev_mondo_tail",
16 "res_error_head", "res_error_tail",
17 "nres_error_head", "nres_error_tail",
19 "cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"),
23 isa_fields
= isa_fields
.get(isa
, [])
25 for sec
in cpt
.sections():
28 re_cpu_match
= re
.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec
)
29 # Search for all the execution contexts
33 if re_cpu_match
.group(2) != "0":
34 # This shouldn't happen as we didn't support checkpointing
35 # of in-order and O3 CPUs.
36 raise ValueError("Don't know how to migrate multi-threaded CPUs "
40 for fspec
in isa_fields
:
41 for (key
, value
) in cpt
.items(sec
, raw
=True):
43 isa_section
.append((key
, value
))
45 name
= "%s.isa" % re_cpu_match
.group(1)
46 isa_sections
.append((name
, isa_section
))
48 for (key
, value
) in isa_section
:
49 cpt
.remove_option(sec
, key
)
51 for (sec
, options
) in isa_sections
:
52 # Some intermediate versions of gem5 have empty ISA sections
53 # (after we made the ISA a SimObject, but before we started to
54 # serialize into a separate ISA section).
55 if not cpt
.has_section(sec
):
59 raise ValueError("Unexpected populated ISA section in old "
62 for (key
, value
) in options
:
63 cpt
.set(sec
, key
, value
)