util/m5/m5op_x86.S

   1 /*
   2  * Copyright (c) 2003-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <gem5/asm/generic/m5ops.h>
  30
  31 /*
  32   Note: The ABI for pseudo ops using the M5OP_ADDR is defined in
  33   src/arch/x86/pseudo_inst_abi.hh. If the ABI is changed below, it's likely
  34   that the ABI in the arch directory will also need to be updated.
  35
  36   The ABI for the magic instruction-based pseudo ops is not affected by this.
  37 */
  38
  39 #if defined(M5OP_ADDR) && defined(M5OP_PIC)
  40 /* Use the memory mapped m5op interface */
  41 #define TWO_BYTE_OP(name, number)         \
  42         .globl name;                      \
  43         .func name;                       \
  44 name:                                     \
  45         mov m5_mem@gotpcrel(%rip), %r11;  \
  46         mov (%r11), %r11;                 \
  47         mov $number, %rax;                \
  48         shl $8, %rax;                     \
  49         mov 0(%r11, %rax, 1), %rax;       \
  50         ret;                              \
  51         .endfunc;
  52
  53 #elif defined(M5OP_ADDR) && !defined(M5OP_PIC)
  54 /* Use the memory mapped m5op interface */
  55 #define TWO_BYTE_OP(name, number)         \
  56         .globl name;                      \
  57         .func name;                       \
  58 name:                                     \
  59         mov m5_mem, %r11;                 \
  60         mov $number, %rax;                \
  61         shl $8, %rax;                     \
  62         mov 0(%r11, %rax, 1), %rax;       \
  63         ret;                              \
  64         .endfunc;
  65
  66 #else
  67 /* Use the magic instruction based m5op interface. This does not work
  68  * in virtualized environments.
  69  */
  70
  71 #define TWO_BYTE_OP(name, number)         \
  72         .globl name;                      \
  73         .func name;                       \
  74 name:                                     \
  75         .byte 0x0F, 0x04;                 \
  76         .word number;                     \
  77         ret;                              \
  78         .endfunc;
  79
  80 #endif
  81
  82 TWO_BYTE_OP(m5_arm, M5OP_ARM)
  83 TWO_BYTE_OP(m5_quiesce, M5OP_QUIESCE)
  84 TWO_BYTE_OP(m5_quiesce_ns, M5OP_QUIESCE_NS)
  85 TWO_BYTE_OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE)
  86 TWO_BYTE_OP(m5_quiesce_time, M5OP_QUIESCE_TIME)
  87 TWO_BYTE_OP(m5_rpns, M5OP_RPNS)
  88 TWO_BYTE_OP(m5_wake_cpu, M5OP_WAKE_CPU)
  89 TWO_BYTE_OP(m5_exit, M5OP_EXIT)
  90 TWO_BYTE_OP(m5_fail, M5OP_FAIL)
  91 TWO_BYTE_OP(m5_init_param, M5OP_INIT_PARAM)
  92 TWO_BYTE_OP(m5_load_symbol, M5OP_LOAD_SYMBOL)
  93 TWO_BYTE_OP(m5_reset_stats, M5OP_RESET_STATS)
  94 TWO_BYTE_OP(m5_dump_stats, M5OP_DUMP_STATS)
  95 TWO_BYTE_OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS)
  96 TWO_BYTE_OP(m5_checkpoint, M5OP_CHECKPOINT)
  97 TWO_BYTE_OP(m5_read_file, M5OP_READ_FILE)
  98 TWO_BYTE_OP(m5_write_file, M5OP_WRITE_FILE)
  99 TWO_BYTE_OP(m5_debug_break, M5OP_DEBUG_BREAK)
 100 TWO_BYTE_OP(m5_switch_cpu, M5OP_SWITCH_CPU)
 101 TWO_BYTE_OP(m5_add_symbol, M5OP_ADD_SYMBOL)
 102 TWO_BYTE_OP(m5_panic, M5OP_PANIC)
 103 TWO_BYTE_OP(m5_work_begin, M5OP_WORK_BEGIN)
 104 TWO_BYTE_OP(m5_work_end, M5OP_WORK_END)
 105 TWO_BYTE_OP(m5_dist_toggle_sync, M5OP_DIST_TOGGLE_SYNC)