misc: merge branch 'release-staging-v19.0.0.0' into develop
[gem5.git] / util / minorview / minor.pic
1 # Copyright (c) 2013 ARM Limited
2 # All rights reserved
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
23 #
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #
36 # minor.pic: Pipeline appearance of the Minor pipeline for minorview
37
38 # Markup of the pipeline blocks.
39 # '>' and '<' are connecting arrows.
40 # '/', ':' and '\' mark multi-line arrows.
41 # All other (non-space) character rectangles are the shapes of the
42 # corresponding blocks below the markup.
43
44 <<<
45 IPIPIPIPIPIPIPIPIP LSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLS KKKKKKKKKK
46 IP IP LS LS KK KK
47 IPiririr-\itititIP LSimimim drdrdr-\dtdtdtdt sbsbsbsbsbsbLS KK KK
48 IPiririr-/itititIP LSimimim drdrdr-/dtdtdtdt sbsbsbsbsbsbLS KK KK
49 IPIPIPIPIPIPIPIPIP LSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLS KK KK
50 KK KK
51 KK KK
52 acacac sasasasasasasasa EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE KK KK
53 acacac sasasasasasasasa EE EE KK KK
54 EEscscscscscscscscscscscscscscscscscscscEE KK KK
55 EEscscscscscscscscscscscscscscscscscscscEE KK KK
56 EE EE KK KK
57 F1F1F1F1-\1212-\F2F2F2F2-\2D2D-\DDDD-\DEDE-\EEiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqEE KK KK
58 F1 F1 :1212 :F2 F2 :2D2D :DDDD :DEDE :EEiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqEE KK KK
59 F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EE EE KK KK
60 F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EEEiEiEiEi f0f0f0f0f0f0f0f0f0f0f0 ccccEE KK KK
61 F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EEEiEiEiEi f0f0f0f0f0f0f0f0f0f0f0 ccccEE KK KK
62 F1fefeF1 :1212 :F2fifiF2-/2D2D-/DDDD-/DEDE-/EEEiEiEiEi f1f1f1f1f1f1f1f1f1f1f1 ccccEE KKKKKKKKKK
63 F1fefeF1 :1212 :F2fifiF2 DDDD EEEiEiEiEi f1f1f1f1f1f1f1f1f1f1f1 ccccEE
64 F1fefeF1-/1212-/F2fifiF2 DDDD EEEiEiEiEi f2f2f2f2f2f2f2f2f2f2f2 ccccEE
65 b2b2-\F1fefeF1 -\F2fifiF2 DDDD EEEiEiEiEi f2f2f2f2f2f2f2f2f2f2f2 ccccEE-\b1b1
66 b2b2-/F1fefeF1 -/F2fifiF2 DDDD EEEiEiEiEi f3f3f3f3f3f3f3f3f3f3f3 ccccEE-/b1b1
67 F1fefeF1/-2121/-F2fifiF2 DDDD EEEiEiEiEi f3f3f3f3f3f3f3f3f3f3f3 ccccEE
68 F1F1F1F1\-2121\-F2F2F2F2 DDDD EEEiEiEiEi f4f4f4f4f4f4f4f4f4f4f4 ccccEE
69 EEEiEiEiEi f4f4f4f4f4f4f4f4f4f4f4 ccccEE
70 FiFiFiFi DiDiDiDi EE f5f5f5f5f5f5f5f5f5f5f5 ccccEE
71 Fi Fi Di Di EE f5f5f5f5f5f5f5f5f5f5f5 ccccEE
72 FiFiFiFi DiDiDiDi EE f6f6f6f6f6f6f6f6f6f6f6 ccccEE
73 EE f6f6f6f6f6f6f6f6f6f6f6 ccccEE
74 EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
75 >>>
76
77 # Macros for block type appearance. Macros are expanded in the 'block'
78 # lines below and can include other macros.
79 #
80 # Attributes are name=value pairs.
81 # Available names (and valid values);
82 #
83 # shape: {fifo, box, openBottom}
84 # stripDir: {vert, horiz}
85 # stripOrd: {RL, LR}
86 # decoder: {insts, lines, branch, dcache, counts}
87 # border: {thin, mid, thick}
88 # dataElement: <name>
89 # hideId: ({T, S, P, L, F, E})*
90 # name: <string>
91 # colours: ({U, B, -, E, R, F, r, w, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9})*
92 # type: {key, block}
93
94 # macro fifo: shape=fifo stripDir=vert
95 macro fifo: shape=openBottom stripDir=horiz stripOrd=RL border=mid
96 macro fu: decoder=insts border=mid name="" nameLoc=left
97 # macro back: decoder=back border=mid dataElement=space name=""
98 macro prediction: decoder=branch border=mid dataElement=prediction name=""
99 macro forward: border=mid name=""
100 macro dcache: fifo decoder=dcache dataElement=addr
101 macro icache: fifo decoder=lines
102 macro cacheFrame: stripDir=vert decoder=frame blankStrips=5 \
103 dataElement=in_tlb_mem
104 macro activity: decoder=counts shorten=2 border=mid
105 macro inputBuffer: name="inputBuffer" fifo
106 macro seqNum: decoder=counts border=mid
107 macro streamFrame: decoder=frame stripDir=vert dataElement=streamSeqNum
108 macro predictionFrame: decoder=frame stripDir=vert dataElement=predictionSeqNum
109
110 # Block descriptions:
111 # description ::= <char>: <unit-name-in-trace>
112 # ( {<macro-name>, <name>=<value> )*
113 # name ::= ? alphanumeric name with dots ?
114 # value ::= "(<char-except-">)*", <char-except-' '>* }
115
116 Fi: fetch2.inputBuffer0 inputBuffer decoder=lines
117 Di: decode.inputBuffer0 inputBuffer decoder=insts hideId=E
118 Ei: execute.inputBuffer0 inputBuffer stripDir=horiz decoder=insts border=mid
119 F1: fetch1 streamFrame blankStrips=11 name="Fetch1"
120 fe: fetch1 decoder=lines border=thin name="Line"
121 F2: fetch2 predictionFrame blankStrips=11 name="Fetch2"
122 fi: fetch2 decoder=insts border=thin name="Insts"
123 DD: decode decoder=insts name="Decode"
124 EE: execute streamFrame blankStrips=21 name="Execute"
125 cc: execute decoder=insts name="Commit" border=mid
126 12: f1ToF2 forward decoder=lines
127 21: f2ToF1 prediction
128 2D: f2ToD forward decoder=insts hideId=E
129 DE: dToE forward decoder=insts
130 b1: eToF1 forward decoder=branch
131 b2: eToF1 forward decoder=branch
132 IP: fetch1 cacheFrame name="Fetch queues"
133 LS: execute.lsq cacheFrame name="LSQ"
134 ir: fetch1.requests icache name="Requests"
135 it: fetch1.transfers icache name="Transfers"
136 dr: execute.lsq.requests dcache name="Requests"
137 dt: execute.lsq.transfers dcache name="Transfers"
138 sb: execute.lsq.storeBuffer dcache name="Store buffer"
139 KK: _ type=key colours="UB-ERFrw0123456789"
140 f0: execute.fu.0 fu shorten=2 name=Int
141 f1: execute.fu.1 fu shorten=2 name=Int
142 f2: execute.fu.2 fu shorten=2 name=Mul
143 f3: execute.fu.3 fu shorten=2 name=Div
144 f4: execute.fu.4 fu shorten=2 name=Float
145 f5: execute.fu.5 fu shorten=2 name=Mem
146 f6: execute.fu.6 fu shorten=2 name=Misc
147 iq: execute.inFlightInsts0 fifo decoder=insts name="inFlightInsts"
148 im: execute.inFUMemInsts0 fifo decoder=insts name="inFU..."
149 sc: execute.scoreboard0 name="scoreboard" decoder=indexedCounts \
150 dataElement=busy border=mid name="scoreboard" strips=38 stripelems=3
151 sa: activity dataElement=stages activity name="Stage activity"
152 ac: activity dataElement=activity decoder=counts border=mid name="Activity"